1. Field of the Invention
This invention relates generally to the field of integrated circuits. More particularly, the invention relates to an improved architecture for detecting and repairing logic blocks within integrated circuits.
2. Description of the Related Art
Random access memory (“RAM”) devices are typically fabricated with several redundant columns or rows of memory so that, in the event that a memory cell within the memory device fails, the redundant row or column may be used in place of the row or column with the damaged memory cell. This concept will be described with respect to FIG. 1, which shows a representative portion of a memory device 100 with a damaged memory cell 120. Within the memory device 100, adjacent pairs of memory columns are provided as inputs to each of a plurality of multiplexers 140-144. For example, adjacent memory columns 121 and 122 are each provided as inputs to multiplexer 142 which couples one of the two memory columns 121, 122 to its output based on selection signals 130.
In operation, the memory device 100 is tested following fabrication. Typically, during testing, a known test pattern is shifted through each of the memory cells to determine whether the cells are functional. If a memory device with damaged cells is determined to be repairable (i.e., based on the number and/or location of the damaged memory cells) the memory columns on which the damaged memory cells are located are disabled. In the example shown in FIG. 1, based on the location of the damaged memory cells, one or more fuses within a fuse bank 105 are blown. A decoder 110 decodes the output of the fuse bank to identify and bypass the memory column 121 with the damaged memory cell 120. A single fuse within the fuse bank 105 represents either a binary ‘1’ or a ‘0’ depending on whether it is blown. Thus, with N fuses configured within the fuse bank 105, 2N memory columns may be individually identified by the decoder 110. Although the select signal 130 from the decoder 110 is illustrated as a single line in FIG. 1 for simplicity, the decoder output will actually include a separate binary control line for supplying a select signal to each of the multiplexers.
In the specific example illustrated in FIG. 1, in response to the blown fuses, the decoder 110 generates a select signal of ‘0’ for multiplexer 142, causing the multiplexer 142 to select memory column 122 in lieu of the damaged memory column 121. The decoder 110 also provides binary select signals of ‘0’ to all multiplexers 143-144 to the right of multiplexer 142, causing these multiplexers 143-144 to select the rightmost memory columns at each of their respective inputs. Conversely, the decoder 110 provides a binary select signal of ‘1’ to each of the multiplexers 140-141 to the left of multiplexer 142, causing these multiplexers 140-141 to select the leftmost memory columns at each of their respective inputs. Thus, the end result is that the memory column 122 with the damaged memory cell 120 is effectively removed from the memory device 100.